Recommended Design Practices
Transmission lines. EMI
often becomes issues when you try to get the FCC certification for your
product. Transmission lines dramatically reduce EMI, because transmission
lines are constructed to keep returning signal current close to the outgoing
signal path. The magnetic fields from the two currents cancel each other.
The typical transmission lines on PCB are microstrip (traces on the top and
bottom layers) and stripline (traces on the inner layers).
minimize the reflection of signals on the board, terminations are recommended.
Source terminations are normally used in CMOS and TTL logic design, because
they do not require high sink/source current. CMOS and TTL drivers usually
only can sink/source maximum 24mA current. End terminations are normally
used in the ECL and PECL logic design. SSTL2 logic (e.g. DDR interface)
requires both source and end terminations.
Clock distribution. Clock
toggles faster than other signals, and connects every flip-flop on the
board. It has to be distributed carefully to ensure the system work
properly. To minimize the reflection, every clock line should employs a
source terminator. The value of the termination resistor depends on the
number of clock lines and trace impedance. The length of the each clock line
should be the same t minimize the clock skew. Thus it requires the trace
length matching in the layout.
Power distribution. Power
plane is highly recommended to minimize the voltage drop across the board.
Ground plane is highly recommended to minimize the common-path noise
voltages. Place bypass capacitors close to the power supplies output pins
for board level filtering, and also place bypass capacitors close to the
power pins of each chip for local filtering. Use low ESR bypass capacitors
to minimize the power voltage ripples.
PCI and PCIe bus. The
clock trace length should be less than 2" from the card edge to the
chip input pin. The length of each AD bus line should be the same. The
differential pair of the RX, TX and clock of PCIe should be length-matched.
Board stacking. The way
of stacking the PCB board is very important for impedance control. Below is
a typical 62mil thick 10-layer PCB stacking (6 layers signals and 4
layers power/ground) with uniform impedance on both micro strip lines and
Large Scale FPGA Design
Design with a synchronous
clock. The logic clouds need a synchronous clock to optimize the
timing closure. Make sure the main clock is fan-outted by a global clock
buffer. Avoid to use local clocks in the design.
Design with a synchronous
reset. An asynchronous reset from external world can be spurious resets due to noise or glitches on the board or system reset. If these spurious reset pulses occur near a clock edge, the flip-flops can go metastable. A reset synchronizer is recommended to be employed. A reset synchronizer can be a pair of
cascaded flip-flops reset by the asynchronous reset and synchronized by the global
clock. The synchronized reset drives through the a reset global buffer to the rest of the
flip-flops in the design.
Pipeline stages. To
achieve the desired high-speed logic design, pipeline stages are recommended
to add. One example would be the realization of FIR filter. A number of MAC
(Multiply-Accumulate) operations needs to be used. The data computing path
needs to be broken down into multiple pipeline stages to achieve the
Offset constraints. One
the circuit board often the FPGA interfaced with external devices such as
memory chips, CPU bus, other FPGAs etc. To successfully interface with the
external devices, the setup and hold time has to be met. Specifying offset
constraints in the constrain file will ensure to meet the setup and hold
time when FPGA talks to the external devices.
I/O pads. There are
flip-flops and delay elements inside I/O pads. Generally-speaking you want
to ensure the FPGA input and output signals are registered inside the I/O
pads for achieving the best timing. You may also intentionally turn on/off
the delay elements to adjust the timing. You may examine the place and route
results inside the I/O pads by using the vendor provided tools such as
Xilinx FPGA editor.
Multi Pass Place and Route.
Sometimes the single pass place and route does not create the best possible
timing. You may chose multiple pass place and route option by specifying the
number of passes and the cost table value, which save the best place and
route results on the computer.
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