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Cable Set-Top Box Video Security Processor

  • The security processor for cable set-top box is designed by using Xilinx Spartan3 FPGA with embedded Micro Blaze microprocessor.
  • The FPGA is a SOC (system on chip) which includes Micro Blaze 32-bit RISC microprocessor, SHA (security harsh algorithm) engine, 3DES encryption engine, DMA controller, interrupt controller, SDRAM controller, flash controller, dual-port RAM, MIPS. microprocessor interface, DCM, block RAM, etc. 
  • The design resources used include ISE, EDK, Coregen, Platform Studio, FPGA editor, ChipScope, Verilog, VHDL, PERL, TCL, and ModelSim.  

Cable Set-Top Box Video Packet Processor

  • The video processor for cable set-top box is designed by using Altera Cyclone FPGA.
  • The FPGA design includes IP multicast/unicast filters, MPEG packets, PID, MoCA interface controller, DMA controller, interrupt controller, dual-port RAM, PLL, RAM block, etc. 
  • The design resources used include Quartus, Megafunction, SignalTap, Verilog, VHDL, PERL, TCL, and ModelSim.  

PCIe Based Cable Head-End Encryption Card 

  • The PCI express based cable head-end data encryption card consists of 2.5GHz high-speed PCB board design and FPGA design. 
  • The board level design includes Xilinx Spartan 3E1600, PCIe physical layer chip, smart card chips, high-efficient switching power suppliers, 2.5GHz PCIe bus, 250MHz Phy layer bus, transmission line, impedance control and trace length matching. 
  • The FPGA consists of Xilinx PCIe end point core, user application backend engine, RX and TX DMA engines, FIFO, block RAM, DCM, vector based interrupt controller, smart card interface etc. 
  • Design resources used include ISE, Verilog, VHDL, PERL, TCL, Synplicity, Synopsys VCS, Cadence allegro.

PCI 64-bit/66MHz Based Digital Video Recorder 

  • The ultra-fast (4 CIF/480IPS) security digital video recording (DVR) card consists of high-speed PCB board design and FPGA design. It DMAs 16 channels video data to the server memory in real time. 
  • The board level design includes 64-bit/66MHz PCI bus, million-gates Virtex II FPGA, DDR, video amp, 16-ch video decoders, video encoder, switching power supplies, power on reset circuit, transmission line, impedance control and trace length matching etc. 
  • The FPGA consists of PCI64bit/66MHz core, PCI initiator and target, PCI DMA core, user backend application, DCM, PLL, time-sliced multi-I2C cores.
  • Design resources used include ISE, FPGA editor, Coregen, ChipScope, ModelSim, PERL, TCL, Verilog, VHDL, Synplicity, and Hyperlynx.

Satellite Terminal  

  • The Intel StrongArm SA110 (32-bit RISC processor, 230Mhz) based satellite TDMA circuit board consists of high-speed PCB board design and FPGA design.
  • The board level design includes CPU, system controller, 10/100 Based Ethernet MAC and physical layer, PCI bus, Flash memory, SDRAM and controller, Altera FPGAs, programmable timers and interrupt controllers, UARTs, watch dog/RTC, reset circuit, power supply,  transmission line and impedance control. 
  • Design resources used include Verilog, PERL, TCL, XL-Verilog, Signalscan, Silos, FPGA compiler, Timing designer, MAX+PLUS II, ARM SDK and VxWorks. 

ASIC Prototyping

  • The satellite modem ASIC is prototyped by the million-gates FPGAs (Xilinx Virtex). 
  • The FPGA consists of ARM bus controller (ASB), timer, interrupt controller, UART, ADC/DAC control, LED/HEX display, Mailbox, Synthesizer/PLL controller, PA Ramp controller, RX & TX filter chains, Decimator/Interpolator (FIR type), QPSK, and AGC/AFC controller, Encoder, Decoder, De/Scrambler. 
  • Design resources used include Cadence Verilog-XL and Signalscan, Silos, Synopsis DC_Shell, PERL, TCL, FPGA compiler and Design manager. 

Disk Drive Header Tester

  • Disk drive MR head measurement system consists of high-speed PCB board design and FPGA design. 
  • The board level design includes frequency synthesizer (1 GHz), DDS, PLL,  current generator, precision DACs, FPGA, I2C bus, amplifier, power supply, Altera FPGAs, pattern generator, TTL, CMOS, PECL, impedance match, trace termination.  

DSP Based Seismic Data Acquisition System

  • Designed TI DSP (TMS320C30) based embedded system circuit board for real-time seismic data acquisition and processing application. 
  • Design includes TI DSP chip, real-time OS, data acquisition ping-pong scheme, digital FIR filters, decimation, data re-construction  in C and ASM, 16-ch delta-sigma ADC, DRAM, SRAM, EPROM, FPGA, UART, interrupt controller, timer/counter, DMA etc. Two US patents are issued for this design.

Wireless Pager  

  • Designed medical pager product for hospital application. 
  • Design includes 8051 micro-controller, pager receiver, pager decoder, LCD display controller, power supply, power management, flash memory etc. 

Universal iPhone/iPod Charger  

  • PodRescue is a 3-in-1 universal rapid charger and backup battery pack for iPod/iPhone with patent pending technology inside. It provides backup power, or allows you to charge iPod/iPhone via 4 AAA batteries, car cigarette lighter, or wall adapter through the 12V fireWire fast charging instead of the 5V USB slow charging. Works with iPhone, iPod touch, iPod classic, iPod video, iPod mini, and iPod nano. Your music never stop. 
  • Design includes efficient low-cost switching power supplies, power sensor, charging circuit, iPod/iPhone interface, mechanical box design, plastic molding etc. 
Please call us at 760-402-6647 or click here to send us an email to discuss a solution to your design needs.

 

 

 

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